Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of an the output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to "count" the incoming clock cycles.
It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10 .mu.A at a supply voltage of 3.3 V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit.
Existing counters are generally based on binary counters. As the basic unit for a binary counter is a divide-by-two unit, extra logic is required to implement counts by odd numbers or even numbers which are not 2.sup.n, where n is an integer. This extra logic reduces the highest operating frequency obtainable by the counter and also consumes chip area. Moreover, existing binary counters rarely produce an output signal which has a 50% duty cycle when dividing by odd integers.
Signals having a 50% duty cycle are particularly desirable because in such signals, there is the maximum possible time for the rising and falling edges to complete. This avoids pulse shrinkage, both in terms of amplitude and timing of the signal, which can result in duty cycles which are significantly different from 50%, and which may affect the overall timing as a result. Moreover, many circuits use both the rising and falling edges of a clock signal, so that it can be advantageous to provide the falling edge midway through the cycle of rising edges.
An additional problem with existing binary counters is that those which operate with high speed, low power, and with short signal paths are generally not easily programmable to divide by different integers other than the one by which they are basically constructed to divide, particularly when these integers are odd integers.